ESD Circuits, ESD Standards Overview for the Device Testing Technologist
Latch-up Physics & Design, impact of CMOS Scaling on ESD HCPh

Date: July 14-15, 2008

The AMD Commons Bldg, One AMD Place, Sunnyvale, CA

• Lunch and refreshments provided.

ESD Circuits*
July 14, 2008, 8:30 a.m. - 4:30 p.m.
instructors: Timothy J. Maloney, Intel Corporation; Steven H. Vvoldman, Steven H. Voldman LLC;
Eugene Worley, Chronicle Technology, Inc.

Standards Overview for the Device Testing Technologist* July 15, 2008, 8:30 a.m. - Noon
Instructor: Leo G. Henry, ESD-TLP Consultants

Latch-up Physics & Design July 15, 2008, 1:00 p.m. - 2:30 p.m.
Steven Steven H. Voldman LLC

Impact of CMOS Technology Scaling on HCPh July 15, 2008, 3:00 p.m. - 4:30 p.m.
Steven Steven H. Voldman LLC

Offered by the

ESD Association

7900 Turin Rd., Bldg. 3 Rome, NY 13440-2069, USA

Download Flyer Here (pdf)