Silicon  Valley EOS/ESD 

Meeting  Reminder: 7-21-2010 @5:30 pm 
 

 SiVA is BACK!

July 21:  Modern On-Chip ESD Active Clamp Design

Rosario Consiglio, President & CEO of Impulse Semiconductor, Inc., will discuss developments in On-Chip ESD Active Clamp Designs.

·        Modern IC designs use “active” ESD clamps for on-chip protection.  If your IC design must pass the three key ESD product qualification specifications:

1.      2,000V Human Body Model (HBM)

2.      200V Machine Model (MM)

3.      500V Charged Device Model (CDM)

then you must have a properly optimized active ESD Clamp!

·        Active clamp design and GDSII layout techniques will be discussed for digital and analog applications to include PLL, XAUI, SATA and PCIE protection. 

·        Circuit simulation optimization over-process and temperature will be covered along with active clamp design errors.  

October 20:  Measurement and Monitoring Methods for CDM ESD Sensitivity Testing

·        Industry veteran Arnie Steinman will provide an overview of what is added to the standard static control program to control CDM discharges to ESD-sensitive devices in test, assembly, packaging and contract manufacturing.  He will focus on measurements that demonstrate the success of the program in eliminating ESD hazards, and methods for their calibration. 

·        An ESDA member since 1984, Arnie has served on the Board of Directors, Standards Committee, and many standards workgroups, including ionization, automated handlers and cleanrooms.  As Chief Technology Officer at Ion Systems, Arnie was a principal author of most international ionization standards, and has advised IEST, NEBB, and JACA on cleanroom electrostatic issues.  Since 1995 Steinman has led the SEMI ESD Task Force on electrostatic issues in semiconductor manufacturing.

Sincerely, 
 
 Leo G. Henry, Ph. D                   Wayne Tan

Vice President                             President

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